Porous wire-in-tube structures

ABSTRACT

A method for fabricating porous wire-in-tube (WiT) nanostructures including forming a first porous core-shell nanostructure, forming a second porous core-shell nanostructure by increasing thickness and porosity of the porous core-shell nanostructure, and forming a porous WiT nanostructure by etching the second porous core-shell nanostructure. Forming the first porous core-shell nanostructure may include forming a porous layer on a semi-conductive core by depositing a first plurality of particles on the semi-conductive core and generating an initial porous semi-conductive core by etching the semi-conductive core simultaneously with forming the porous layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority from pending U.S.Provisional Patent Application Ser. No. 62/742,290, filed on Oct. 6,2018, and entitled “SI-BASED POROUS WIRE-IN-TUBE NANOSTRUCTURES FORLITHIUM-ION BATTERIES,” which is incorporated herein by reference in itsentirety.

TECHNICAL FIELD

The present disclosure generally relates to wire-in-tube structures,particularly to porous wire-in-tube nanostructure, and more particularlyto a method and a system for fabricating porous wire-in-tubenanostructures.

BACKGROUND

Nanostructures have recently attracted great attention due to theirexceptional chemical, physical, and electrical properties. Among varioustypes of nanostructures, hollow nanostructures are of great interestbecause of superior properties including high surface area, low density,and high permeability. Therefore, using hollow nanostructures with largesurface areas and short diffusion paths in lithium-ion batteries (LIBs)may effectively aid in tolerating large volume variation upon severalcycles of charging/discharging due to their void space and provide moreaccessible sites between active materials and electrolytes to improvecycling stability and electrochemical reaction rate.

One-dimensional (1D) hollow nanostructures have grasped significantinterest because apart from their large specific surface area and largeinterior void space, they may be conceived as potential building blocksin various fields such as ion-transport channels, water desalinationprocesses, and especially energy storage devices. Also, one-dimensional(1D) semi-conductive hollow nanostructures have already been fabricatedwith high control over their dimensions and surface chemicalcompositions.

Moreover, it is believed that one-dimensional hollow nanostructures withhighly porous walls may show improved electrochemical performances incomparison to their solid counterparts. However, the development of 1Dhollow nanostructures coupled with highly porous walls remains achallenge. As a promising 1D material, various studies have beenconducted on the fabrication of porous Al₂O₃ nanostructures and porousAl₂O₃ core-shell structures using atomic layer deposition (ALD)technique.

However, the ALD technique is an expensive method and demands furtherex-situ steps to create hollow nanostructures. Thus, there is a need fora simple and cost-effective method and an effective system forfabricating porous wire-in-tube nanostructures with tunable hollowness.Moreover, there is a need for porous wire-in-tube (WiT) nanostructureswith adjustable electrochemical properties.

SUMMARY

This summary is intended to provide an overview of the subject matter ofthe present disclosure and is not intended to identify essentialelements or key elements of the subject matter, nor is it intended to beused to determine the scope of the claimed implementations. The properscope of the present disclosure may be ascertained from the claims setforth below in view of the detailed description below and the drawings.

In one general aspect, the present disclosure describes an exemplarymethod for fabricating porous wire-in-tube (WiT) nanostructures. Theexemplary method may include forming a first porous core-shellnanostructure, forming a second porous core-shell nanostructure byincreasing thickness and porosity of the first porous core-shellnanostructure, and forming a porous WiT nanostructure by etching thesecond porous core-shell nanostructure. In an exemplary embodiment,forming the first porous core-shell nanostructure may include forming aporous layer on a semi-conductive core by depositing a first pluralityof particles on the semi-conductive core and generating an initialporous semi-conductive core by etching the plurality of unmasked regionsof the semi-conductive core simultaneously with forming the porouslayer. In an exemplary embodiment, forming the porous layer may includeobtaining a plurality of unmasked regions.

In an exemplary embodiment, increasing thickness and porosity of thefirst porous core-shell nanostructure may include repeating an iterativeprocess until the thickness of the porous layer reaches a predefinedthreshold. In an exemplary embodiment, the iterative process may includeincreasing the thickness of the porous layer by depositing a secondplurality of particles on the semi-conductive core and generating asecondary porous semi-conductive core by etching the plurality ofunmasked regions of the initial porous semi-conductive coresimultaneously with depositing the second plurality of particles.

In an exemplary embodiment, depositing the first plurality of particleson the semi-conductive core may include generating a plurality of metalparticles by placing a metal electrode in a plasma environment withplasma power between about 100 W and about 300 W and sputtering theplurality of metal particles on the semi-conductive core by exposing theplurality of metal particles to a mixture of O₂/H₂ gases. In anexemplary embodiment, placing the metal electrode in the plasmaenvironment may include placing at least one of an aluminum (Al)electrode, and a titanium (Ti) electrode in the plasma environment. Inan exemplary embodiment, exposing the plurality of metal particles tothe mixture of O₂/H₂ gases may include introducing the mixture of O₂/H₂gases to the plurality of metal particles for duration between about 10seconds and about 100 seconds.

In an exemplary embodiment, etching the plurality of unmasked regions ofthe semi-conductive core simultaneously with forming the porous layermay include exposing the porous layer to a mixture of O₂/H₂ and afluorine-containing gas for less than about 7 seconds. In an exemplaryembodiment, etching the plurality of unmasked regions of thesemi-conductive core simultaneously with forming the porous layer mayinclude introducing a mixture of O₂/H₂/SF₆ gases to the porous layer. Inan exemplary embodiment, etching the seoncdary porous semi-conductivecore may include exposing the secondary porous semi-conductive core to afluorine-containing gas for duration between about 10 seconds and about50 seconds with a flow rate between about 100 sccm and about 300 sccmand plasma power between about 100 W and about 300 W.

In an exemplary embodiment, repeating the iterative process until thethickness of the porous layer reaches the predefined threshold mayinclude repeating the iterative process until the thickness of theporous layer reaches a value less than about 1000 nm. In an exemplaryembodiment, repeating the iterative process until the thickness of theporous layer reaches the predefined threshold may include repeating theiterative process until the thickness of the porous layer reaches avalue between about 1 nm and about 20 nm.

In an exemplary embodiment, depositing the porous layer on thesemi-conductive core may include depositing the porous layer on at leastone of a silicon core, a germanium core, and combinations thereof. In anexemplary embodiment, depositing the porous layer on the semi-conductivecore may include depositing the porous layer with nanosized pores on thesemi-conductive core. In an exemplary embodiment, depositing the porouslayer on the semi-conductive core may include depositing the porouslayer on a nanowire with a diameter between about 10 nm and about 500nm.

In another general aspect, the present disclosure describes an exemplarysystem for fabricating porous wire-in-tube (WiT) nanostructures. Theexemplary system may include a main chamber, a gas source of a pluralityof gas sources, a gas inlet, a gas valve of a plurality of gas valves, avacuum pump, a radiofrequency generator, a memory, and one or moreprocessors. In an exemplary embodiment, the main chamber may include asubstrate for holding a semi-conductive core and a pair of parallelmetal electrodes. In an exemplary embodiment, the pair of parallel metalelectrodes may include a top electrode configured to generate aplurality of metal particles and a ground electrode configured to holdthe substrate.

In an exemplary embodiment, the gas source may be configured to containat least one gas of a plurality of gases. In an exemplary embodiment,the plurality of gases may include O₂, H₂, and a fluorine-containinggas. In an exemplary embodiment, the fluorine-containing may includesulfur hexafluoride (SF₆). In an exemplary embodiment, the gas inlet maybe configured to introduce a mixture of the plurality of gases into themain chamber. In an exemplary embodiment, the gas valve may beconfigured to couple the gas inlet with a respective gas source of theplurality of gas sources.

In an exemplary embodiment, the vacuum pump may be configured togenerate a vacuum inside the main chamber. In an exemplary embodiment,the radiofrequency generator may be configured to generate a plasmaenvironment with plasma power between about 100 W and about 300 W in thevacuum. In an exemplary embodiment, the memory may haveprocessor-readable instructions stored therein. In an exemplaryembodiment, one or more processors may be configured to access thememory and execute the processor-readable instructions, which, whenexecuted by the one or more processors configures the one or moreprocessors to perform the exemplary method for fabricating the porousWiT nanostructures.

In another general aspect, the present disclosure describes an exemplarywire-in-tube (WiT) nanostructure. The exemplary WiT nanostructure mayinclude a porous nanotube, a semi-conductive nanowire embedded insidethe porous nanotube, and a gap between the porous nanotube and thesemi-conductive nanowire. In an exemplary embodiment, the porousnanotube may have a thickness between about 1 nm and about 20 nm and thesemi-conductive nanowire may have a diameter between about 10 nm andabout 500 nm. In an exemplary embodiment, the porous nanotube mayinclude at least one of alumina, titanium dioxide, and combinationsthereof. In an exemplary embodiment, the semi-conductive nanowire mayinclude at least one of silicon, germanium, and combinations thereof. Inan exemplary embodiment, the porous nanotube may include an amorphousstructure. In an exemplary embodiment, the semi-conductive nanowire mayinclude a crystalline structure.

Other exemplary systems, methods, features, and advantages of theimplementations will be or will become, apparent to one of ordinaryskill in the art upon examination of the following figures and detaileddescription. It is intended that all such additional systems, methods,features, and advantages be included within this description and thissummary, be within the scope of the implementations and be protected bythe claims herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawing figures depict one or more implementations in accord withthe present teachings, by way of example only, not by way of limitation.In the figures, like reference numerals refer to the same or similarelements.

FIG. 1A shows a flowchart of an exemplary method for fabricating porouswire-in-tube nanostructures, consistent with one or more exemplaryembodiments of the present disclosure.

FIG. 1B shows a flowchart of an exemplary method for forming porouscore-shell nanostructures, consistent with one or more exemplaryembodiments of the present disclosure.

FIG. 1C shows a flowchart of an exemplary method for depositing aplurality of particles on a semi-conductive core, consistent with one ormore exemplary embodiments of the present disclosure.

FIG. 1D shows a flowchart of an exemplary method for increasingthickness and porosity of the porous core-shell nanostructure,consistent with one or more exemplary embodiments of the presentdisclosure.

FIG. 2 shows a schematic representation of an exemplary porouswire-in-tube nanostructure, consistent with one or more exemplaryembodiments of the present disclosure.

FIG. 3 shows a schematic representation of an exemplary system forfabricating wire-in-tube nanostructures, consistent with one or moreexemplary embodiments of the present disclosure.

FIG. 4 shows a high-level functional block diagram of a processor,consistent with one or more exemplary embodiments of the presentdisclosure.

FIG. 5A shows an array of silicon nanowires (SiNWs) on a siliconsubstrate, consistent with one or more exemplary embodiments of thepresent disclosure.

FIG. 5B shows tilted view (45°) of a scanning electron microscope (SEM)image of SiNWs grown on a silicon substrate through a vapor-liquid-solid(VLS) mechanism, consistent with one or more exemplary embodiments ofthe present disclosure.

FIG. 5C shows an array of porous SiNW-Al₂O₃ core-shell nanostructures ona silicon substrate, consistent with one or more exemplary embodimentsof the present disclosure.

FIG. 5D shows an array of porous SiNW-Al₂O₃ wire-in-tube nanostructureson a silicon substrate, consistent with one or more exemplaryembodiments of the present disclosure.

FIG. 5E shows an array of hollow Al₂O₃ nanotubes on a silicon substrate,consistent with one or more exemplary embodiments of the presentdisclosure.

FIG. 6A shows SEM images of products fabricated with different etchingtimes, consistent with one or more exemplary embodiments of the presentdisclosure.

FIG. 6B shows an SEM image of an etching process of WiT nanostructure, amagnified view of two sections of WiT nanostructure, and a 5-foldmagnified image of WiT nanostructure with scallops on the sidewalls ofthe SiNW, consistent with one or more exemplary embodiments of thepresent disclosure.

FIG. 7A shows a transmission electron microscopy (TEM) image of thickAl₂O₃ hollow nanotubes, consistent with one or more exemplaryembodiments of the present disclosure.

FIG. 7B shows a transmission electron microscopy (TEM) image of thinAl₂O₃ hollow nanotubes, consistent with one or more exemplaryembodiments of the present disclosure.

FIG. 7C shows a TEM image of a porous Al₂O₃ hollow nanotube, consistentwith one or more exemplary embodiments of the present disclosure.

FIG. 8A shows a tilted view of an SEM image of an array of exemplary WiTmicrostructures, consistent with one or more exemplary embodiments ofthe present disclosure.

FIG. 8B shows tilted view SEM images of an array of Al₂O₃ hollowmicrotubes, a 2-fold magnified view, and a 10-fold magnified view of ahollow microtube, consistent with one or more exemplary embodiments ofthe present disclosure.

FIG. 9A shows an SEM image and energy-dispersive X-ray spectroscopy(EDS) elemental mapping of Si, Al, and O of an exemplary wire-in-tube(WiT) nanostructure, consistent with one or more exemplary embodimentsof the present disclosure.

FIG. 9B shows energy-dispersive X-ray spectroscopy (EDS) spectrum ofpassivated SiNWs, consistent with one or more exemplary embodiments ofthe present disclosure.

FIG. 9C shows an EDS spectrum of Al₂O₃ hollow nanotubes, consistent withone or more exemplary embodiments of the present disclosure.

FIG. 10A shows a TEM image of a WiT nanostructure of Si-in-Al₂O₃,consistent with one or more exemplary embodiments of the presentdisclosure.

FIG. 10B shows an HR-TEM image of the interface between the alumina NTshell and the SiNW core, consistent with one or more exemplaryembodiments of the present disclosure.

FIG. 10C shows an HR-TEM image of the SiNW core and its magnified view,consistent with one or more exemplary embodiments of the presentdisclosure.

FIG. 10D shows an HR-TEM image of the interface between the SiNW coreand the alumina NT shell, consistent with one or more exemplaryembodiments of the present disclosure.

FIG. 11 shows a Raman spectra comparison of SiNWs as a template, SiNWspassivated, and Al₂O₃NTs, consistent with one or more exemplaryembodiments of the present disclosure.

FIG. 12 shows low-resolution and high-resolution X-ray photoelectronspectroscopy (XPS) survey spectra of SiNWs as a template, consistentwith one or more exemplary embodiments of the present disclosure.

FIG. 13A shows low-resolution XPS survey spectra of SiNWs passivatedduring 140 iterations, consistent with one or more exemplary embodimentsof the present disclosure.

FIG. 13B shows high-resolution XPS survey spectra of SiNWs passivatedduring 140 iterations, consistent with one or more exemplary embodimentsof the present disclosure.

FIG. 14 shows low-resolution and high-resolution XPS survey spectra ofAl₂O₃ hollow NTs processed under 25 s etching time, consistent with oneor more exemplary embodiments of the present disclosure.

FIG. 15 shows X-ray diffraction (XRD) patterns of SiNWs, WiTnanostructures which are SiNWs passivated with Al during 140 iterations,and hollow Al nanotubes obtained after 25 seconds of etching time,consistent with one or more exemplary embodiments of the presentdisclosure.

FIG. 16A shows a microscopic half-cell diagram of an exemplarylithium-based ion battery (LIB) including exemplary wire-in-tubenanostructures, consistent with one or more exemplary embodiments of thepresent disclosure.

FIG. 16B shows a schematic representation of a cross-sectional view anda top view of exemplary WiT nanostructure for SEI formation duringlithiation/delithiation process, consistent with one or more exemplaryembodiments of the present disclosure.

FIG. 17 shows voltammogram (CV) curves of first, second, and 5^(th)cycles at a scan rate of about 1 mV s⁻¹, consistent with one or moreexemplary embodiments of the present disclosure.

FIG. 18 shows galvanostatic charge/discharge voltage profiles of anexemplary WiT nanostructure for 1^(st), 2^(nd), and 5^(th) cycles at arate of C/16, consistent with one or more exemplary embodiments of thepresent disclosure.

FIG. 19A shows cycling stability and coulombic efficiency of anexemplary WiT nanostructure at a C/16 rate density for 30 cycles,consistent with one or more exemplary embodiments of the presentdisclosure.

FIG. 19B shows cycling stability and coulombic efficiency of anexemplary WiT nanostructure at 1C and 4C rate densities for 100 cycles,consistent with one or more exemplary embodiments of the presentdisclosure.

FIG. 20 shows galvanostatic charge/discharge voltage profiles of anexemplary WiT nanostructure for 1^(st), 2^(nd), and 100^(th) cycles at arate of 1C, consistent with one or more exemplary embodiments of thepresent disclosure.

FIG. 21 shows a rate capability test under a variable current rate ofC/4 to 12C with 4 cycles at each C-rate and a first cycle at C/4,consistent with one or more exemplary embodiments of the presentdisclosure.

FIG. 22 shows a comparison between average coulombic efficiency andcapacity retention of exemplary WiT nanostructures for 100 cycles withdifferent etching times, consistent with one or more exemplaryembodiments of the present disclosure.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are setforth by way of examples in order to provide a thorough understanding ofthe relevant teachings. However, it should be apparent that the presentteachings may be practiced without such details. In other instances,well-known methods, procedures, components, and/or circuitry have beendescribed at a relatively high-level, without detail, in order to avoidunnecessarily obscuring aspects of the present teachings.

The following detailed description is presented to enable a personskilled in the art to make and use the methods and devices disclosed inexemplary embodiments of the present disclosure. For purposes ofexplanation, specific nomenclature is set forth to provide a thoroughunderstanding of the present disclosure. However, it will be apparent toone skilled in the art that these specific details are not required topractice the disclosed exemplary embodiments. Descriptions of specificexemplary embodiments are provided only as representative examples.Various modifications to the exemplary implementations will be readilyapparent to one skilled in the art, and the general principles definedherein may be applied to other implementations and applications withoutdeparting from the scope of the present disclosure. The presentdisclosure is not intended to be limited to the implementations shownbut is to be accorded the widest possible scope consistent with theprinciples and features disclosed herein.

Disclosed herein is an exemplary method and system for fabricatingexemplary porous wire-in-tube structures by etching a semi-conductivecore simultaneously with depositing a porous layer on thesemi-conductive core. The exemplary method may provide a process totransform an array of vertical or slanted nanowires into differentproducts including core-shell nanostructures, wire-in-tube (WiT)nanostructures, and hollow nanotubes by adjusting the etching anddeposition conditions. FIG. 1A shows a flowchart of the exemplary methodfor fabricating exemplary porous wire-in-tube (WiT) nanostructures,consistent with one or more exemplary embodiments of the presentdisclosure. An exemplary method 100 may include forming a first porouscore-shell nanostructure (step 102), forming a second porous core-shellnanostructure by increasing thickness and porosity of the first porouscore-shell nanostructure (step 103), and forming a porous WiTnanostructure by etching the secondary porous semi-conductive core ofthe second porous core-shell nanostructure (step 104).

In further detail with respect to step 102, in an exemplary embodiment,the first porous core-shell nanostructure may include a shell withnanosized pores. In an exemplary embodiment, step 102 may be alsoimplemented to form porous core-shell microstructures. FIG. 1B shows aflowchart of an exemplary method for forming the first porous core-shellnanostructure, consistent with one or more exemplary embodiments of thepresent disclosure. In an exemplary embodiment, FIG. 1B illustratesdetails of the forming step 102 of FIG. 1A. Referring to FIG. 1B,forming the first porous core-shell nanostructure may include forming aporous layer on a semi-conductive core by depositing a first pluralityof particles on the semi-conductive core (step 106) and generating aninitial porous semi-conductive core of the first porous core-shellnanostructure by etching the semi-conductive core simultaneously withforming the porous layer (step 108).

In further detail with respect to step 106, in an exemplary embodiment,depositing the first plurality of particles on the semi-conductive coremay include obtaining a plurality of unmasked regions on thesemi-conductive core. In an exemplary embodiment, each of the pluralityof unmasked regions may include a portion of a surface of thesemi-conductive core and the surface maybe not covered by one or more ofthe first plurality of particles. In an exemplary embodiment, formingthe porous layer on the semi-conductive core may include forming theporous layer on at least one of a silicon core, a germanium core, andcombinations thereof.

In an exemplary embodiment, forming the porous layer on thesemi-conductive core may include forming the porous layer with athickness between about 1 nm and 20 nm on the semi-conductive core. Inan exemplary embodiment, forming the porous layer on a semi-conductivecore may include forming the porous layer with nanosized pores. In anexemplary embodiment, forming the porous layer on a semi-conductive coremay include forming the porous layer on at least one of a nanowire, ananorod, and combinations thereof. In an exemplary embodiment, thenanowire may have with a diameter between about 10 nm and about 500 nm.

FIG. 1C shows a flowchart of an exemplary method for depositing thefirst plurality of particles on a semi-conductive core, consistent withone or more exemplary embodiments of the present disclosure. FIG. 1Cillustrates details of the depositing step 106 of FIG. 1B. Referring toFIG. 1C, depositing the first plurality of particles on thesemi-conductive core may include generating a plurality of metalparticles by exposing a metal electrode to a plasma environment (step110) and sputtering the plurality of metal particles on thesemi-conductive core by exposing the plurality of metal particles to amixture of O₂/H₂ gases (step 112).

In further detail with respect to step 110, in an exemplary embodiment,generating a plurality of metal particles may include placing a metalelectrode in a plasma environment. In an exemplary embodiment, exposingthe metal electrode to the plasma environment may include placing themetal electrode in the plasma environment with a plasma power betweenabout 100 W and about 300 W. In an exemplary embodiment, exposing themetal electrode to the plasma environment may include placing at leastone of an aluminum (Al) electrode, and a titanium (Ti) electrode in theplasma environment.

In further detail with respect to step 112, in an exemplary embodiment,sputtering the plurality of metal particles on the semi-conductive coremay include exposing the plurality of metal particles to a mixture ofO₂/H₂ gases. As used herein, “exposing the plurality of metal particlesto a mixture of O₂/H₂ gases” may refer to putting the plurality of metalparticles in contact with a mixture of O₂/H₂ gases. In an exemplaryembodiment, exposing the plurality of metal particles to the mixture ofO₂/H₂ gases may include adding the mixture of O₂/H₂ gases to theplurality og metal particles using through a gas inlet. In an exemplaryembodiment, exposing the plurality of metal particles to the mixture ofO₂/H₂ gases may include introducing the mixture of O₂/H₂ gases to theplurality of metal particles for duration between about 10 seconds andabout 100 seconds.

Referring back to FIG. 1B, in further detail with respect to step 108,in an exemplary embodiment, generating the initial poroussemi-conductive core by etching the semi-conductive core simultaneouslywith forming the porous layer may include etching the plurality ofunmasked regions of the semi-conductive core simultaneously with formingthe porous layer. In an exemplary embodiment, etching the plurality ofunmasked regions of the semi-conductive core simultaneously with formingthe porous layer may include exposing the porous layer to a mixture ofO₂/H₂ and a fluorine-containing gas.

As used herein, “exposing porous layer to a mixture of O₂/H₂ and afluorine-containing gas” may refer to putting the porous layer incontact with a mixture of O₂/H₂ and a fluorine-containing gas. In anexemplary embodiment, exposing the porous layer to the mixture of O₂/H₂and a fluorine-containing gas may include adding the mixture of O₂/H₂and a fluorine-containing gas to the porous layer. In an exemplaryembodiment, exposing the porous layer to the mixture of O₂/H₂ and afluorine-containing gas may include introducing the mixture of O₂/H₂ anda fluorine-containing gas to the porous layer for duration less thanabout 7 seconds. In an exemplary embodiment, the fluorine-containing gasmay include sulfur hexafluoride (SF₆).

Referring back to FIGS. 1A and 1 n further detail with respect to step103, increasing the thickness and the porosity of the first porouscore-shell nanostructure may include repeating an iterative processuntil the thickness of the porous layer reaches a predefined threshold.In an exemplary embodiment, repeating the iterative process until thethickness of the porous layer reaches the predefined threshold mayinclude repeating the iterative process until the thickness of theporous layer reaches a value less than about 1000 nm. In an exemplaryembodiment, repeating the iterative process until the thickness of theporous layer reaches the predefined threshold may include repeating theiterative process until the thickness of the porous layer reaches avalue between about 1 nm and about 20 nm.

In an exemplary embodiment, the iterative process may include increasingthe thickness of the porous layer by depositing a second plurality ofparticles on the semi-conductive core and generating a secondary poroussemi-conductive core by etching the plurality of unmasked regions of theinitial porous semi-conductive core simultaneously with depositing thesecond plurality of particles. In an exemplary embodiment, the iterativeprocess may be repeated between about 70 and about 180 iterations.

FIG. 1D shows a flowchart of an exemplary method for increasingthickness and porosity of the first porous core-shell nanostructure,consistent with one or more exemplary embodiments of the presentdisclosure. FIG. 1D illustrates details of the depositing step 103 ofFIG. 1A. Referring to FIG. 1D, increasing the thickness and the porosityof the first porous core-shell nanostructure may include increasing thethickness of the porous layer by depositing a second plurality ofparticles on the semi-conductive core (step 114) and generating asecondary porous semi-conductive core of the second porous core-shellnanostructure by etching the plurality of unmasked regions of theinitial porous semi-conductive core simultaneously with depositing thesecond plurality of particles (step 116). In an exemplary embodiment,step 103 may be repetitively performed until the thickness of the porouslayer reaches a predefined threshold less than 1000 nm.

In an exemplary embodiment, the iterative process of step 103 forincreasing the thickness and the porosity of the first porous core-shellnanostructure may be repeated for between about 70 and about 180iterations. In an exemplary embodiment, after each iteration of step 103thickness of the porous layer may be increased due to depositing thesecond plurality of particles on the semi-conductive core and porosityof the porous layer may be increased by etching the plurality ofunmasked regions of the semi-conductive core simultaneously withdepositing the second plurality of particles.

In an exemplary embodiment, in further detail with respect to step 114,increasing the thickness of the porous layer may include depositing thesecond plurality of particles on the semi-conductive core similar tostep 106 of FIG. 1B. In an exemplary embodiment, in further detail withrespect to step 116, generating the secondary porous semi-conductivecore may include etching the plurality of unmasked regions of theinitial porous semi-conductive core simultaneously with depositing thesecond plurality of particles similar to step 108 of FIG. 1B.

Referring back to FIGS. 1A and 1 n further detail with respect to step104, in an exemplary embodiment, forming the porous WiT nanostructuremay include etching the secondary porous semi-conductive core of theporous core-shell structure. In an exemplary embodiment, etching thesecondary porous semi-conductive core may include exposing the secondaryporous semi-conductive core to a fluorine-containing gas for durationbetween about 10 seconds and about 50 seconds.

As used herein, “exposing the seoncdary porous semi-conductive core to afluorine-containing gas” may refer to putting the secondary poroussemi-conductive core in contact with a fluorine-containing gas. In anexemplary embodiment, exposing the secondary porous semi-conductive coreto the fluorine-containing gas may include adding thefluorine-containing gas to the secondary porous semi-conductive core. Inan exemplary embodiment, hollow nanotube with a porous structure may begenerated by etching total silicon content of the secondary poroussemi-conductive core. In an exemplary embodiment, etching time maydepend on the nanowire diameter, and less etching time may correspond tothinner nanowires.

In an exemplary embodiment, exposing the secondary poroussemi-conductive core to a fluorine-containing gas may include exposingthe secondary porous semi-conductive core to SF₆ gas. In an exemplaryembodiment, exposing the secondary porous semi-conductive core to thefluorine-containing gas may include exposing the secondary poroussemi-conductive core to the fluorine-containing gas with a flow ratebetween about 100 standard cubic centimeters per minute (sccm) and about300 sccm. In an exemplary embodiment, exposing the secondary poroussemi-conductive core to the fluorine-containing gas may include exposingthe secondary porous semi-conductive core to the fluorine-containing gasin a plasma environment with a plasma power between about 100 W andabout 300 W.

In an exemplary embodiment, exemplary method 100 may further includeextracting the secondary porous semi-conductive core from the porous WiTnanostructure after etching the secondary porous semi-conductive core.In an exemplary embodiment, extracting the secondary poroussemi-conductive core from the porous WiT nanostructure may includeextracting the secondary porous semi-conductive core through thenanosized pores of the porous layer into the plasma environment.

FIG. 2 shows a schematic representation of an exemplary porouswire-in-tube nanostructure 200, consistent with one or more exemplaryembodiments of the present disclosure. In an exemplary embodiment, theexemplary wire-in-tube nanostructure may include a porous nanotube 202,a semi-conductive nanowire 204 embedded inside porous nanotube 202, anda gap 206 between porous nanotube 202 and semi-conductive nanowire 204.In an exemplary embodiment, exemplary porous wire-in-tube structure 200may be used as a binder-free anode for high capacity and high ratelithium-ion batteries (LIBs). In an exemplary embodiment, porousnanotube 202 may have a thickness between about 1 nm and about 20 nm. Inan exemplary embodiment, porous nanotube 202 may include least one ofalumina, titanium dioxide, and combinations thereof. In an exemplaryembodiment, the porous nanotube 202 may have an amorphous structure.

In an exemplary embodiment, the semi-conductive nanowire 204 may includeat least one of silicon, germanium, and combinations thereof. In anexemplary embodiment, the semi-conductive nanowire 204 may have adiameter between about 10 nm and about 500 nm. In an exemplaryembodiment, the semi-conductive nanowire 204 may have a crystallinestructure. In an exemplary embodiment, the semi-conductive nanowire 204with a length of at least about 20 μm.

FIG. 3 shows a schematic representation of an exemplary system 300 forimplementing exemplary method 100 for fabricating wire-in-tubenanostructures 200, consistent with one or more exemplary embodiments ofthe present disclosure. In an exemplary embodiment, different steps ofmethod 100 may be implemented by utilizing an exemplary system 300.Exemplary system 300 may be a reactive-ion deposition and etching (RIDE)system including a capacitively-coupled plasma (CCP) reactor as a mainchamber 302, a plurality of gas sources 304, a gas inlet 306, aplurality of gas valves 308, a vacuum pump 310, a radiofrequency source312, and computer unit 314. In an exemplary embodiment, system 300 maybe a reactive ion deposition and etching (RIDE) system.

In an exemplary embodiment, the main chamber 302 may include a substrate316 and a pair of parallel metal electrodes 318 and 320. In an exemplaryembodiment, substrate 316 may hold a semi-conductive core 322. In anexemplary embodiment, the pair of parallel metal electrodes may includea top electrode 318 configured to generate a plurality of metalparticles to form a porous layer on a semi-conductive core and a groundelectrode 320 configured to hold substrate 316. In exemplaryembodiments, pair parallel metal electrodes 318 and 320 may be locatedat top and bottom sides of main chamber 302, respectively.

In an exemplary embodiment, a gas source of plurality of gas sources 304may be configured to contain at least one gas of a plurality of gases.In an exemplary embodiment, the plurality of gases may include O₂, H₂,and a fluorine-containing gas. In an exemplary embodiment, gas inlet 306may be configured to introduce a mixture of the plurality of gases intomain chamber 302. In an exemplary embodiment, a gas valve of pluralityof gas valves 308 may be configured to couple gas inlet 306 with arespective gas source of the plurality of gas sources 304. In anexemplary embodiment, system 300 may further include a mass flowcontroller 326 configured to set a flow rate of a mixture of theplurality of gases inside main chamber 302.

In an exemplary embodiment, vacuum pump 310 may be configured togenerate a vacuum inside main chamber 302. In an exemplary embodiment,radiofrequency generator 312 may be a 13.56 MHz radiofrequency generatorconfigured to generate a plasma environment with plasma power between100 W and 300 W in the vacuum. In an exemplary embodiment, system 300may further include a pressure transducer 324 configured to set apressure value inside main chamber 302.

In an exemplary embodiment, computer unit 314 may include a memoryhaving processor-readable instructions stored therein; and one or moreprocessors configured to access the memory and execute theprocessor-readable instructions, which, when executed by the one or moreprocessors configures the one or more processors to perform an exemplarymethod 100.

In an exemplary embodiment, depositing the plurality of particles on thesemi-conductive core (step 106) may include generating a plurality ofmetal particles by exposing top electrode 318 to the plasma environmentand sputtering the plurality of metal particles on semi-conductive core322. In an exemplary embodiment, sputtering the plurality of metalparticles on semi-conductive core 322 may include exposing the pluralityof metal particles to a mixture of O₂ and H₂ for duration between about10 seconds and about 100 seconds by adjusting each respective gas valveof the plurality of gas valves 308.

In an exemplary embodiment, etching the plurality of unmasked regions ofsemi-conductive core 322 simultaneously with forming the porous layer(step 108) may include exposing the porous layer to a mixture of O₂, H₂,and a fluorine-containing gas for duration less than about 7 seconds byadjusting each respective gas valve of the plurality of gas valves 308.In an exemplary embodiment, etching the secondary porous semi-conductivecore (step 104) may include exposing the secondary poroussemi-conductive core to the fluorine-containing gas with a flow ratebetween about 100 sccm and about 300 sccm for duration between about 10seconds and about 50 seconds by adjusting each respective gas valve ofthe plurality of gas valves 308.

FIG. 4 shows a high-level functional block diagram of an exemplarycomputer unit 400 in which an embodiment of the present disclosure, orportions thereof, may be implemented as computer-readable code,consistent with exemplary embodiments of the present disclosure. Forexample, method 100 may be implemented in computer unit 400 usinghardware, software, firmware, tangible computer-readable media havinginstructions stored thereon, or a combination thereof and may beimplemented in one or more. Hardware, software, or any combination ofsuch may embody any of the modules and components in FIGS. 1A-3.

If programmable logic is used, such logic may execute on a commerciallyavailable processing platform or a special purpose device. One ordinaryskill in the art may appreciate that an embodiment of the disclosedsubject matter can be practiced with various processor configurations,including multi-core multiprocessor systems, minicomputers, mainframecomputers, computers linked or clustered with distributed functions, aswell as pervasive or miniature computers that may be embedded intovirtually any device.

For instance, a computing device having at least one processor deviceand a memory may be used to implement the above-described embodiments. Aprocessor device may be a single processor, a plurality of processors,or combinations thereof. Processor devices may have one or moreprocessor “cores.”

An embodiment of the invention is described in terms of this examplecomputer unit 400. After reading this description, it will becomeapparent to a person skilled in the relevant art how to implement theinvention using other processors and/or computer architectures. Althoughoperations may be described as a sequential process, some of theoperations may, in fact, be performed in parallel, concurrently, and/orin a distributed environment, and with program code stored locally orremotely for access by single or multi-processor machines. In addition,in some embodiments, the order of operations may be rearranged withoutdeparting from the spirit of the disclosed subject matter.

Processor device 404 may be a special purpose or a general-purposeprocessor device. As will be appreciated by persons skilled in therelevant art, processor device 404 may also be a single processor in amulti-core/multiprocessor system, such system operating alone, or in acluster of computing devices operating in a cluster or server farm.Processor device 404 may be connected to a communication infrastructure406, for example, a bus, message queue, network, or multi-coremessage-passing scheme.

In an exemplary embodiment, computer unit 400 may include a displayinterface 502, for example, a video connector, to transfer data to adisplay unit 430, for example, a monitor. Computer unit 400 may alsoinclude a main memory 408, for example, random access memory (RAM), andmay also include a secondary memory 410. Secondary memory 410 mayinclude, for example, a hard disk drive 412, and a removable storagedrive 414. Removable storage drive 414 may include a floppy disk drive,a magnetic tape drive, an optical disk drive, a flash memory, or thelike. Removable storage drive 414 may read from and/or write to aremovable storage unit 418 in a well-known manner. Removable storageunit 418 may include a floppy disk, a magnetic tape, an optical disk,etc., which may be read by and written to by removable storage drive414. As will be appreciated by persons skilled in the relevant art,removable storage unit 418 may include a computer-usable storage mediumhaving stored therein computer software and/or data.

In alternative implementations, secondary memory 410 may include othersimilar means for allowing computer programs or other instructions to beloaded into computer unit 400. Such means may include, for example, aremovable storage unit 422 and an interface 420. Examples of such meansmay include a program cartridge and cartridge interface (such as thatfound in video game devices), a removable memory chip (such as an EPROM,or PROM) and associated socket, and other removable storage units 422and interfaces 420 which allow software and data to be transferred fromremovable storage unit 422 to computer unit 400.

Computer unit 400 may also include a communications interface 424.Communications interface 424 allows software and data to be transferredbetween computer unit 400 and external devices. Communications interface424 may include a modem, a network interface (such as an Ethernet card),a communications port, a PCMCIA slot, and card, or the like. Softwareand data transferred via communications interface 424 may be in the formof signals, which may be electronic, electromagnetic, optical, or othersignals capable of being received by communications interface 424. Thesesignals may be provided to communications interface 424 via acommunications path 426. Communications path 426 carries signals and maybe implemented using wire or cable, fiber optics, a phone line, acellular phone link, an RF link or other communications channels.

In this document, the terms “computer program medium” and “computerusable medium” are used to generally refer to media such as removablestorage unit 418, removable storage unit 422, and a hard disk installedin hard disk drive 412. Computer program medium and computer usablemedium may also refer to memories, such as main memory 408 and secondarymemory 410, which may be memory semiconductors (e.g. DRAMs, etc.).

Computer programs (also called computer control logic) are stored inmain memory 408 and/or secondary memory 410. Computer programs may alsobe received via communications interface 424. Such computer programs,when executed, enable computer unit 400 to implement differentembodiments of the present disclosure as discussed herein. Inparticular, the computer programs, when executed, enable processordevice 404 to implement the processes of the present disclosure, such asthe operations in method 100 illustrated by flowchart 100 of FIG. 1Adiscussed above. Accordingly, such computer programs representcontrollers of computer unit 400. Where an exemplary embodiment ofmethod 100 is implemented using software, the software may be stored ina computer program product and loaded into computer unit 400 usingremovable storage drive 414, interface 420, and hard disk drive 412, orcommunications interface 424.

Embodiments of the present disclosure also may be directed to computerprogram products including software stored on any computer useablemedium. Such software, when executed in one or more data processingdevice, causes a data processing device to operate as described herein.An embodiment of the present disclosure may employ any computer useableor readable medium. Examples of computer useable mediums include, butare not limited to, primary storage devices (e.g., any type of randomaccess memory), secondary storage devices (e.g., hard drives, floppydisks, CD ROMS, ZIP disks, tapes, magnetic storage devices, and opticalstorage devices, MEMS, nanotechnological storage device, etc.).

The embodiments have been described above with the aid of functionalbuilding blocks illustrating the implementation of specified functionsand relationships thereof. The boundaries of these functional buildingblocks have been arbitrarily defined herein for the convenience of thedescription. Alternate boundaries can be defined so long as thespecified functions and relationships thereof are appropriatelyperformed.

EXAMPLES Example 1: Fabrication of the Exemplary Wire-in-TubeNanostructure

In this example, the exemplary wire-in-tube nanostructures werefabricated through an exemplary method similar to method 100. At first,SiNWs were grown on a silicon (Si) substrate using a chemical vapordeposition (CVD) method. The Si substrate was coated with a thin layerof gold with a thickness between about 5 nm and about 10 nm before SiNWsynthesis. After that, the gold-coated substrate was placed in alow-pressure chemical vapor deposition (LPCVD) reactor at a basepressure of about 2.5 mTorr and at a temperature of about 600° C. Duringthe early stages of the SiNW growth, the gold (Au) layer was convertedinto Au—Si droplets which act as a catalyst for the subsequent steps.The growth of SiNWs was initiated after introducing silane (SiH4) as asilicon precursor with a flow rate of about 20 standard cubiccentimeters per minute (sccm). In this process, the growth of the SiNWswas based on a vapor-liquid-solid (VLS) mechanism.

FIG. 5A shows an array of silicon nanowires (SiNWs) 500 grown on a Sisubstrate, consistent with one or more exemplary embodiments of thepresent disclosure. Referring to FIG. 5A, there is a bright spot of goldnanoparticles 502 at the tip of SiNWs 500. The gold nanoparticles 502were used as the catalyst for the growth of SiNWs 500. FIG. 5B showstilted view (45°) of a scanning electron microscope (SEM) image of SiNWsgrown on a Si substrate through a vapor-liquid-solid (VLS) mechanism,consistent with one or more exemplary embodiments of the presentdisclosure. Referring to FIG. 5B, the SiNWs have a diameter betweenabout 10 nm and about 500 nm. The growth direction of SiNWs is mostlyalong <111> and <110> planes. It should be noted that by controlling thegrowth parameters, such as the thickness of the catalyst layer, growthtime, and reactor pressure, the diameter of the SiNWs may be tuned.

In the next step, first porous core-shell nanostructures of SiNWs inporous alumina (Al₂O₃) tubes were formed by forming a porous Al₂O₃ layeron the SiNW by depositing a plurality of particles on the SiNW andgenerating a porous SiNW by etching the SiNW. Forming the porousSiNW-Al₂O₃ core-shell nanostructures included two sub-steps which werecalled passivation steps. The passivation steps consisted of forming aporous Al₂O₃ nanotube by depositing a porous Al₂O₃ layer on a surface ofeach SiNW which obtained a plurality of unmasked regions on each SiNWand generating a porous SiNW by etching the plurality of unmaskedregions of each SiNW simultaneously with depositing the porous Al₂O₃layer. In order to form the porous Al₂O₃ nanotubes embedding each SiNW,the silicon nanowires (SiNWs) were loaded into system 300 as describedin FIG. 3. The system 300 which was used in this example included acapacitively coupled plasma (CCP) reactor where two parallel aluminum(Al) plates were located at top and bottom sides.

In the RIDE system, the SiNWs were exposed to three gases entailingoxygen, hydrogen, and sulfur hexafluoride (SF₆), in a programmablecontrol manner and in a plasma environment. It may be assumed that ahigh flow rate of hydrogen during two passivation steps may beresponsible for the deposition of a thin and conformal layer of aluminaaround each SiNW. Since the top and bottom electrodes in the etchingsetup were made of aluminum (Al), aluminum was randomly sputtered on theSiNWs in the plasma environment through an electrode bombardmentprocess.

In the first passivation step and after loading SiNWs into the RIDEsystem, an ultrathin porous Al₂O₃ layer with a thickness between about 4nm and about 8 nm was deposited on the surface of the SiNWs throughintroducing a mixture of O₂/H₂ gases to the reactor with duration ofabout 23 seconds and a plasma power of about 200 W. As a result ofdeposition, an amorphous Al₂O₃ layer was deposited and a plurality ofunmasked regions was created on the surface of SiNWs which was notcovered by Al₂O₃.

In the second passivation step, a concurrent mixture of O₂/SF₆/H₂ gaseswas flown into the reactor with duration of about 5 seconds and a plasmapower of about 200 W. The presence of SF₆ during the second passivationstep was responsible for etching the unmasked regions of the SiNWs whichmade the SiNWs porous. Therefore, using SF₆ along H₂ during the secondpassivation step resulted in simultaneous deposition of Al₂O₃ andetching of the SiNW.

In the next step, second porous SiNW-Al₂O₃ core-shell nanostructures wasformed by increasing thickness and porosity of the first porousSiNW-Al₂O₃ core-shell nanostructures through repeating an iterativeprocess until the thickness of the porous Al₂O₃ layer reached a value ofabout 18 nm. The iterative process included sequentially repeating thefirst passivation step and the second passivation step for about 140iterations.

FIG. 5C shows an array of porous SiNW-Al₂O₃ core-shell nanostructures504 on the silicon substrate, consistent with one or more exemplaryembodiments of the present disclosure. Referring to FIG. 5C, there isouter shell 506 which is an ultrathin porous Al₂O₃ layer around eachSiNW 500.

In the next step, a porous Si-in-Al₂O₃ wire-in-tube (WiT) nanostructurewas formed by etching the SiNW of the second porous core-shellnanostructure. During the etching step which takes between about 15seconds and about 25 seconds, only the SF₆ plasma was used to partiallyremove the Si content of each SiNW. The plasma power was set at about180 W and the flow rate of SF₆ was about 150 sccm. It should be notedthat etching time may be set based on the diameter of the synthesizedSiNWs.

During the etching step, free Si content was extracted through nanosizedpores of the porous Al₂O₃ layer by fluorine ions present in a plasmaenvironment of the RIDE system. Therefore, the nanosized pores on thesurfaces of the alumina nanotube were the extraction sites for theetched silicon content. After performing the etching step and extractingthe free Si content, WiT nanostructures including the SiNWs in hollowAl₂O₃ nanotubes with porous structures were obtained. FIG. 5D shows anarray of porous Si-in-Al₂O₃WiT nanostructures 508 on a siliconsubstrate, consistent with one or more exemplary embodiments of thepresent disclosure. Referring to FIG. 5D, porous Si-in-Al₂O₃ WiTnanostructures 508 includes partially etched SiNWs 510 in hollow Al₂O₃nanotubes 512 with porous structures.

By continuing the etching step, the total silicon content of porousSi-in-Al₂O₃ WiT nanostructures 508 was extracted and fully hollow Al₂O₃nanotubes with a porous structure were obtained. FIG. 5E shows an arrayof hollow Al₂O₃ nanotubes 514 on a silicon substrate, consistent withone or more exemplary embodiments of the present disclosure. Referringto FIGS. 5D-5E, porous SiNW-Al₂O₃WiT nanostructures 508 and hollow Al₂O₃nanotubes 514 were well-aligned and preserved the orientation and lengthof SiNWs 500 as shown in FIG. 5A. Also, gold nanoparticles 502 remainintact during the etching and passivation steps.

FIG. 6A shows SEM images of nanostructures fabricated with an etchingtime of about 10 seconds 600, about 18 seconds 602, and about 25 seconds604, consistent with one or more exemplary embodiments of the presentdisclosure. Referring to FIG. 6A, after 10 seconds of etching, unmaskedregions of the SiNW 600 are exposed to the SF₆ gas and Si content wouldbe extracted from unmasked regions 606 which are the first zones of theextraction. After 18 seconds of etching, extraction progresses to allaround of the side walls in the unmasked regions and the Si contentdecreases which forms a wire-in-tube (WiT) nanostructure 602. After 25seconds of etching, the whole silicon content is extracted while thealumina nanotube may be unaltered, and hollow alumina nanotube 604 isformed.

FIG. 6B shows an SEM image of an etching process of WiT nanostructure608, a magnified view of two sections 610 of WiT nanostructure 608, anda 5-fold magnified image of exemplary WiT nanostructure 608 withscallops on the core sidewalls 612, consistent with one or moreexemplary embodiments of the present disclosure. Referring to FIG. 6B,WiT nanostructure 608 and its magnified view 610 show the uniformity ofthe SiNW within the porous Al₂O₃ tube. Also, presence of scallops 614 inthe sidewalls of WiT nanostructure 612 indicates strong local electricalfields at the edge of porous alumina nanotube 616 which causes an ionbowing phenomenon.

It should be noted that based on the diameter of the SiNWs, the aluminananotubes may have different diameters. For instance, FIGS. 7A and 7Bshow thick and thin alumina nanotubes. FIG. 7A shows a transmissionelectron microscopy (TEM) image of thick Al₂O₃ hollow nanotubes,consistent with one or more exemplary embodiments of the presentdisclosure. Referring to FIG. 7A, Al₂O₃ nanotube 700 has a diameter ofabout 130 nm with a hollow structure. FIG. 7B shows a transmissionelectron microscopy (TEM) image of thin Al₂O₃ hollow nanotubes,consistent with one or more exemplary embodiments of the presentdisclosure. Referring to FIG. 7B, Al₂O₃ nanotubes 702 and 704 havehollow structures with a diameter of about 40 nm and about 18 nm,respectively. FIG. 7C shows a TEM image of porous Al₂O₃ hollownanotubes, consistent with one or more exemplary embodiments of thepresent disclosure. Referring to FIG. 7C, the porous Al₂O₃ hollownanotubes synthesized based on exemplary method 100 have a perforatedstructure with nanosized pores 706.

The exemplary method 100 may also be utilized for fabricating WiTmicrostructures and hollow microtube. FIG. 8A shows tilted view of anSEM image of an array of exemplary WiT microstructures 800 and amagnified WiT microstructure 802, consistent with one or more exemplaryembodiments of the present disclosure. Referring to FIG. 8A, theexemplary WiT microstructures 800 have a uniform structure including ahollow alumina microtube embedding a silicon microwire. FIG. 8B showstilted view SEM images of an array of Al₂O₃ hollow microtubes 804, a2-fold magnified view 806, and a 10-fold magnified view 808 of a hollowmicrotube, consistent with one or more exemplary embodiments of thepresent disclosure. Referring to FIG. 8B, all the Al₂O₃ microtubes arefully hollow and have uniform structures.

Example 2: Elemental Composition of the Exemplary Wire-in-TubeMicrostrcture

In this example, the elemental composition of the exemplary wire-in-tubemicrostructure was analyzed by energy-dispersive X-ray spectroscopy(EDS) method. In order to perform the EDS method, the WiT microstructurewere scratched from the surface on a lacey grid to eliminate Sisubstrate effect. FIG. 9A shows an SEM image 900 and energy-dispersiveX-ray spectroscopy (EDS) elemental mapping of Si 902, Al 904, and O 906of an exemplary wire-in-tube (WiT) microstructure, consistent with oneor more exemplary embodiments of the present disclosure. Referring toFIG. 9A, elemental mapping of Si 902, Al 904, and O 906 of the exemplaryWiT microstructure clearly reveals that the Si wire is located in thecenter of the composite and encapsulated by a thin Al₂O₃ tube. Elementalmapping data also reveal that there is void space between the Si wireand the thin Al₂O₃ tube.

Also, in order to determine the nature of the exemplary WiTnanostructure and the exemplary hollow nanotubes (NTs), theenergy-dispersive X-ray spectroscopy (EDS) analysis was used in TEMmode. FIG. 9B shows EDS spectrum of a passivated SiNW prepared by 140iterations during the passivation step, consistent with one or moreexemplary embodiments of the present disclosure. Referring to FIG. 9B,Si peak 908 is predominant and confirms the fact that the core issilicon, while Al weak peak implies the formation of the passivationlayer on the SiNWs.

FIG. 9C shows an EDS spectrum of Al₂O₃ hollow nanotubes, consistent withone or more exemplary embodiments of the present disclosure. Referringto FIG. 9C, the spectrum of the fully hollow NT clearly illustrates asharp peak of Al 910 which indicates the aluminum and oxygen compositionof the tube and complete removal of the Si core. The relatively strongoxygen peak suggests that the tube region is aluminum oxide.

Example 3: Lattice Structure of the Exemplary Wire-in-Tube Nanostrcture

In this example, the lattice structure of the exemplary WiTnanostructures was examined using high-resolution transmission electronmicroscopy (HR-TEM) analysis. FIG. 10A shows a TEM image of WiTnanostructure 1000 of Si-in-Al₂O₃, consistent with one or more exemplaryembodiments of the present disclosure. Referring to FIG. 10A, the WiTnanostructure 1000 has a diameter of about 120 nm and have three zonesincluding an interface between an alumina NT shell and a SiNW core 1002,the SiNW core 1004, and an interface between the SiNW core and thealumina NT shell 1006.

These three zones of WiT nanostructure 1000 have been studied withhigher resolution imaging. FIG. 10B shows an HR-TEM image of theinterface between the alumina NT shell and the SiNW core 1002,consistent with one or more exemplary embodiments of the presentdisclosure. FIG. 10C shows an HR-TEM image of the SiNW core 1004, and amagnified view 1008 of the HR-TEM of the SiNW core, consistent with oneor more exemplary embodiments of the present disclosure. FIG. 10D showsan HR-TEM image of the interface between the SiNW core and the aluminaNT shell 1006, consistent with one or more exemplary embodiments of thepresent disclosure.

Referring to FIGS. 10B-10D, HR-TEM images demonstrate the crystallinenature of the silicon core, which is sheathed with the amorphous Al₂O₃shell. However, at the interfaces between amorphous alumina nanotube andcrystalline core 1002 and 1004, it is observed that crystallinestructure changes, which is believed to be due to bond formation betweenAl and Si, without bound to any theory. Referring to FIG. 10C, moreanalysis on the lattice image of Si core gives an interplanar spacing of0.32 nm corresponding to Si (111) planes. Therefore, the SiNW coreremains highly crystalline during the etching step, preserving theinitial growth direction. Most of the large nanowires grow in (111)direction while Al₂O₃ shell has an amorphous structure.

Example 4: Raman Spectroscopy, XPS, and XRD Characterization of theExemplary Wire-in-Tube Nanostrcture

In this example, Raman spectroscopy was used to investigate theformation of hollow nanotubes. Raman spectroscopy measurements wereperformed by a micro-Raman spectrometer with an excitation wavelength ofabout 532 nm. All measurements were carried out at room temperature inthe ambient atmosphere. FIG. 11 shows Raman spectra of SiNWs as atemplate (1100), WiT nanostructures of SiNWs passivated during 140iterations of the first and the second passivation steps for increasingthickness and porosity of the porous layer (1102), and Al₂O₃NTsprocessed under 25 seconds of etching time (1104), consistent with oneor more exemplary embodiments of the present disclosure.

Referring to FIG. 11, the high-intensity peaks at 513 cm⁻¹ in 1100 and1102 spectra may be attributed to the silicon content of the SiNW andthe WiT nanostructure, and its intensity drops after the passivation andetching steps. Also, the formation of an alumina nanotube on nanowiresmay be assumed to be responsible for the reduction of the silicon peakat 513 cm⁻¹ in 1102 spectrum as compared to 1100 spectrum. Finally, withthe complete extraction of Si core and formation of NTs, the siliconRaman line vanishes that confirms complete extraction of silicon.Therefore, the significant drop in the silicon intensity peak at 513cm⁻¹ in 1104 spectrum as compared to 1100 spectrum may be due to theremoval of the inner silicon content after the NT formation.

Also, the chemical composition of the outer layers has been furtherinvestigated using an X-ray photoelectron spectroscopy (XPS) analysis.As an internal reference, the C 1 s peak set at 285 eV was used fordetermining absolute binding energies in XPS data. FIG. 12 showslow-resolution (1200) and high-resolution (1202) XPS spectra of SiNWs asa template, consistent with one or more exemplary embodiments of thepresent disclosure. FIG. 13A shows low-resolution XPS spectrum of WiTnanostructures SiNWs passivated during 140 iterations of the first andthe second passivation steps for increasing thickness and porosity ofthe porous layer, consistent with one or more exemplary embodiments ofthe present disclosure.

Referring to FIGS. 12 and 13A, the low-resolution XPS spectrum showsthat the passivation process induces significant changes in the samplecompared to the reference SiNWs sample. The data obtained from theseinvestigations corroborate the evolution of Al₂O₃ nanotubes just afterthe passivation steps. The peak maxima of the O 1 s, Si—O₂ and Si 2pcore levels of SiNWs appear at 532.5, 103.3, and 98.2 eV energies,respectively. Also, Al peaks at 74.8 and 532.4 eV emerge for WiTnanostructures which have been passivated through 140 iterations andrepresent the binding energies of Al 2p and O 1 s, respectively. Thehigher oxidation state of Al in Al₂O₃ compared to metallic Al causes ashift in the binding energy of Al 2p to a higher value of 74.8 eV whichindicates the complete oxidation of Al to Al₂O₃. The latter data are inagreement with the value expected for Al 2p in Al₂O₃.

FIG. 13B shows high-resolution XPS spectra of Al 2p (1300) and Si 2p(1302) regions for WiT nanostructure which are SiNWs passivated during140 iterations, consistent with one or more exemplary embodiments of thepresent disclosure. Referring to FIG. 13B, the high-resolution XPSspectrum 1300 of the Al 2p region confirms the formation of Al—F bondlocated at 76.4 eV. Also, the high-resolution XPS spectrum 1302 of theSi 2p is decomposed into three contributing peaks emerging at around101.2, at 103.1, and 108.4 eV. The peak at 101.2 eV corresponds to Al—Sibond, originating from the reaction of aluminum with the silicon core ofthe inner nanowire which is confirmed by the HR-TEM analysis. The peakat 108.4 eV may be ascribed to oxyfluorinated silicon passivation(SixOyFz). The intense signal around 687.2 eV corresponds to fluorine 1s content.

FIG. 14 shows low-resolution (1400) and high-resolution (1402) XPSspectra of Al₂O₃ hollow NTs obtained after 25 seconds of etching time,consistent with one or more exemplary embodiments of the presentdisclosure. Referring to FIG. 14, the presence of Al—O bonds in the NTsis confirmed by the binding energies of the Al 2p peak at 74.4 eV andthe Al 2 s peak at 120.6 eV. The strongest peak, located at 532.5 eV, isattributed to O 1 s, which originates from Al-0 bonds. The trace valuesof oxygen during the etching step and the presence of the sample in anair ambient would result in complete oxidation of ultrathin layer ofalumina nanotubes. These results corroborate the presence of Al bonds atalumina nanotubes and confirm the assumptions in Al deposition duringthe passivation steps.

In order to understand the structural evolution of SiNWs to hollow NTs,X-ray powder diffraction (XRD) analysis was used for furthercharacterization of these structures at different stages of the tubeformation. FIG. 15 shows X-ray diffraction (XRD) patterns of SiNWs 1500,WiT nanostructures which are SiNWs passivated with Al during 140iterations 1502, and hollow Al nanotubes 1504 obtained after 25 secondsof etching time, consistent with one or more exemplary embodiments ofthe present disclosure.

Referring to FIG. 15, spectrum 1500 of SiNWs shows the presence ofstrong peaks at 28.4°, 47.3°, and 56.4°, which belong to siliconcrystalline planes of (111), (220), and (311). In spectrum 1502 for WiTnanostructures, peaks at 38.3°, 44.6°, 65°, and 78° appear whichcorrespond to Al which occurs as a result of new phase formation betweenAl and Si. The results of XRD analysis seem to be consistent with thedata obtained from HR-TEM and XPS investigations. After the etching stephas been carried out, the inner silicon and any possiblealuminum-silicon constituents were removed and the hollow perforated NTswere obtained. Also, spectrum 1504 confirms disappearing of the aluminumpeaks in hollow NTs. The main silicon peak is due to the remaining partsof the silicon wires and the silicon substrate.

Example 5: Application of the Exemplary Wire-in-Tube Nano Structure inLithium-Ion Batteries

The exemplary WiT nanostructures may be grown directly on stainlesssteel substrates making them suitable as the binder-free anode materialfor lithium-ion batteries (LIBs). The exemplary WiT nanostructures mayeffectively alleviate the structural strain and tolerate the numerousvolume changes of Si wires due to the existence of hollow space in thestructure of WiT nanostructures. Without bound by any theories, it maybe believed that the free outward expansion may be possible for Si wiresbecause of the fact that the outer shell of alumina is mechanicallyrigid and hence significantly reduces the electrode pulverization.Moreover, the porous nanostructure of WiT sidewalls may provide moreaccessible sites to the electrolyte.

FIG. 16A shows a microscopic half-cell diagram of an exemplarylithium-based ion battery (LIB) 1600 including exemplary wire-in-tubenanostructures 1608, consistent with one or more exemplary embodimentsof the present disclosure. Referring to FIG. 16A, the exemplary LIB 1600included a cathode 1602, a separator 1604, and an exemplary anode 1606.Exemplary anode 1606 may include a plurality of wire-in-tubenanostructures 1608.

In exemplary LIB 1600 lithium metal may be used as the counter andreference electrodes and a 1M LiPF₆ solution in a 1:1 (vol %) mixture ofethylene carbonate (EC) and dimethyl carbonate (DMC) may be used as anelectrolyte. Exemplary LIB 1600 is a rechargeable battery in which alithiation/delithiation process is a key electrochemical process fortheir functionality. During lithiation (discharging), the Li⁺ ions flowfrom exemplary anode 1606 to cathode 1602 through an electrolyte andseparator 1604, while the direction of the Li⁺ ions reverses and Li⁺ions flow from cathode 1602 to exemplary anode 1606 during delithiation(charging) when an overvoltage is applied.

During lithiation/delithiation process of the first cycle, a passivationlayer called solid electrolyte interphase (SEI) is formed on surfaces ofexemplary anode 1606 from decomposition of electrolytes. The SEI plays acritical role in the performance of LIBs. The SEI allows Li⁺ transportand blocks electrons in order to prevent further electrolytedecomposition and ensure continued electrochemical reactions. FIG. 16Bshows a schematic representation of a cross-sectional view and a topview of exemplary WiT nanostructure 1608 for SEI formation duringlithiation/delithiation process, consistent with one or more exemplaryembodiments of the present disclosure.

Referring to FIG. 16B, numerous nanosized pores 1614 exist in the porousalumina nanotube 1612 which allow liquid electrolyte to flow inside thehollow structure of exemplary WiT nanostructure 1608 and inundate theSiNW 1610. This seems contradictory because it might violate the wholeconcept of having a stable SEI layer by isolating SiNW 1610 from theliquid electrolyte. However, during lithiation step of first cycle,solid-electrolyte interphase (SEI) layers 1618 forms on the surfaces ofSiNW 1610 and porous alumina nanotube 1612. Then, SiNW 1610 expands dueto lithiation and the expanded SiNW 1616 and the SEI layer 1618 on itssurface touch the inner surface of porous alumina nanotube 1612. Uponthe delithiation step of first cycle, expanded SiNW 1616 shrinks to SiNW1610 and the SEI layers 1618 remains at the inner and outer surfaces ofporous alumina nanotube 1612 and isolates SiNW 1610 from the liquidelectrolyte and only let Li⁺ ions pass through.

After multiple cycles of lithiation/delithiation, the SEI layers 1618may be fully sealed and almost no side reaction occurs between SiNW 1620and the liquid electrolyte. It should be considered that the thicknessof porous alumina nanotube 1612 may be critical because it significantlyimpacts the charge transfer rates. The porous alumina nanotube 1612 maybe thick enough for providing the mechanical and chemical stability ofthe architecture, but, thin enough for decreasing the ionic resistance.Therefore, porous alumina nanotube 1612 shields the SEI from unwantedside reactions in addition to contributing to capacity and helps thestructure to expand freely without damaging the porous alumina nanotube1612.

Example 6: Electrochemical Properties of the Exemplary Wire-in-TubeStructure

In this example, electrochemical properties of the exemplary WiTnanostructure was investigated using this structure as an anode of alithium-ion battery (LIB) in different cycles of charging/discharging.FIG. 17 shows voltammogram (CV) curves of the first cycle 1700, secondcycle 1702, and 5^(th) cycle 1704 at a scan rate of about 1 mV s⁻¹,consistent with one or more exemplary embodiments of the presentdisclosure. Referring to FIG. 17, the characteristic peaks of Si are notdiscernible in the first cycle curve 1700 indicating that Al₂O₃ coatingas a protective layer prevents electrolyte decomposition andsignificantly reduce the formation of the SEI layer. In the curves oflater cycles 1702 and 1704, the magnitude of almost all current peaksincreases and the corresponding CV curves show two small and broadcathodic peaks at around 0.1 and 0.3 V. These peaks are attributed tothe formation of amorphous LixSi phase and the solid-electrolyteinterphase (SEI) layer, respectively.

Referring again to FIG. 17, a sharper cathodic peak is observed at avoltage of about 0.01 V which gradually increases during multiple cyclesof lithiation/delithiation process. This peak may be attributed tocrystalline Li₁₅Si₄. In addition, there are two main peaks in the anodicbranch of CV curves at around 0.35 and 0.55 V, which are characteristicpeaks for amorphous Si, related to different delithiation degrees ofc-Li₁₅Si₄ to a-Lix′ Si and a-Lix′ Si to a-Si. In the following cycles ofCV curves of the exemplary WiT nanostructure, the peak intensitiesincreased, which may be related to the fact that the porous aluminananotube became ionically conductive that effectively conducts lithiumions and blocks electrons. However, the intensity of CV peaks at theuncoated SiNWs may be decreased at the second cycle which is anindication of instability of uncoated SiNW electrode.

Also, the galvanostatic performances of exemplary WiT nanostructureswere examined by employing charge/discharge tests with a potentialwindow of 0.002 to 3 V at various rate densities. FIG. 18 showsgalvanostatic charge/discharge voltage profiles of an exemplary WiTnanostructure between 0.002 and 3.00 V vs Li/Li⁺ for 1^(st) cycle 1800,2^(nd) cycle 1802, and 5th cycle 1804 at a rate of C/16, consistent withone or more exemplary embodiments of the present disclosure. Referringto FIG. 18, galvanostatic charge/discharge voltage profiles indicatehigh initial discharge and charge capacities of 4125 mAh g⁻¹ and 3148mAh g⁻¹ which are close to the theoretical values and yielding acoulombic efficiency (CE) of about 76%.

FIG. 19A shows cycling stability and coulombic efficiency of anexemplary WiT nanostructure at a C/16 rate density for 30 cycles,consistent with one or more exemplary embodiments of the presentdisclosure. Referring to FIG. 19A, after 30 cycles, the capacity ofexemplary WiT nanostructure kept almost steady; so that the chargecapacity reached 3002 mAh g⁻¹ with retention of about 95.4%. Theirreversible capacity in the initial cycle may be attributed to theirreversible alloying with Li, trapped Li⁺ ions in the inner holes ordefects of Si, and the SEI formation. Also, the coulombic efficiency maybe further improved in practical applications by pre-lithiation processof Si-containing anode using solution or electrochemical processes.

The enhanced porosity of Si part of the nanostructures may beresponsible for a high capacity of exemplary WiT nanostructures. Thesepores may act as the active sites for lithium diffusion and enhance theeffective surface area of the Si nanostructures. In addition, the porousalumina nanotube may prevent the degradation of SEI layer at aSi/electrolyte interface. Also, the existence of empty spaces aroundeach Si wire in WiT nanostructures allows facile expansion duringlithiation step and prevents subsequent damages to the alumina nanotubebecause of Si volume changes. The voltage difference between the chargeand discharge plateaus (ΔV) is about 0.3-0.4 V which is comparable tosimilar reports. The voltage difference correlated to the polarizationof the half-cell system (the smaller the ΔV, the lower thepolarization). Further improvements of the polarization may be obtainedby including additives to electrolyte and electrodes to increasecoulombic efficiency and capacity retention by decreasing thepolarization.

FIG. 19B shows cycling stability and coulombic efficiency of anexemplary WiT nanostructure at 1C and 4C rate densities for 100 cycles,consistent with one or more exemplary embodiments of the presentdisclosure. Referring to FIG. 19B, it is observed that the initialcharge capacity of WiT nanostructures is 2832 mAh g⁻¹ at a rate densityof 1 C which exhibits an excellent coulombic efficiency of about 86%.The capacity is reduced to 2739 mAh g⁻¹ after 100 cycles, indicating96.7% capacity retention. When the rate density is increased to 4 C, theWiT nanostructures may still deliver a discharge/charge capacity of ashigh as 2578.4/2245.6 mAh g⁻¹, respectively. This high rate capacitygradually increases to above 2329 mAh g⁻¹ over the first 100 cycles. Thecharge capacity enhancement probably may be ascribed to the highporosity of WiT nanostructures.

Referring again to FIG. 19B, in the first few cycles of a high ratecharge/discharge test, Li ions are not able to diffuse into the activesites of WiTs structure and the effective surface area of the electrodeis reduced. Also, the coulombic efficiency increased to about 97% afterthe three cycles, which is higher than low rate cycling performance.This is probably due to the smaller volume expansion of WiTsnanostructure and more stable SEI layer under the high charge/dischargerate. Therefore, the exemplary WiT nanostructures show=high chargecapacity of 2329 mAh g⁻¹ at a rate density of 4 C after 100 cycles.

FIG. 20 shows galvanostatic charge/discharge voltage profiles of anexemplary WiT nanostructure for 1^(st) cycle 2000, 2^(nd) cycle 2002,and 100th cycle 2004 at a rate of 1C, consistent with one or moreexemplary embodiments of the present disclosure. Referring to FIG. 20,the shape of the voltage profile may not undergo a considerable changefrom the 2^(nd) cycle 2002 to the 100th cycle 2004, indicating thehighly stable performance of exemplary WiT nanostructure.

FIG. 21 shows a rate capability test under a variable current rate ofC/4 to 12C with 4 cycles at each C-rate and a first cycle at C/4,consistent with one or more exemplary embodiments of the presentdisclosure. Referring to FIG. 21, after an initial discharge capacity of3756 mAh g⁻¹ at C/4, the capacity may be found to stabilize at 3681 mAhg⁻¹. Furthermore, cycling at C, 2 C, and 4 C delivers high reversiblecapacities of 3282, 3089, and 2548, respectively. Then, the exemplaryWiT nanostructure may operate at rates as high as 8 C and 12 C whilestill shows a great capacity of 2021 and 1553 mAh g⁻¹ which demonstratethe excellent high rate capability of the exemplary WiT nanostructures.

Referring again to FIG. 21, when the C rate is returned step by stepfrom 12 C to C/4 again, the original capacity is largely recovered ineach level, revealing the robustness and stability of the exemplary WiTnanostructures. Therefore, the stable SEI along with the high porosityand the hollow nature of the WiTs nanostructure allows outstanding highpower capability. Without bound by any theory, it is believed that thedifference in shape and hollowness of the exemplary WiT nanostructuresmay have an effect on their electrochemical properties.

FIG. 22 shows a comparison between average coulombic efficiency 2200 andcapacity retention 2202 of exemplary WiT nanostructures for 100 cycleswith different etching times, consistent with one or more exemplaryembodiments of the present disclosure. Referring to FIG. 22, exemplaryWiT nanostructures with an etching time of about 18 seconds show thehighest capacity retention among other etching times based on capacityretention 2202 graph. This high capacity retention may be attributed tolarger hollow space in the exemplary WiT nanostructures with 18 secondsof etching time. As the etching time increases, more volume is availableto accommodate large expansion of SiNW during cycling. However, moreetching of SiNW results in weakening of the whole WiT nanostructureleading to loss of electrical contact between Si and substrate after afew cycles and the severe capacity degradation.

Referring again to FIG. 22, the best performance regarding averagecoulombic efficiency was achieved for the WiT nanostructure with 18seconds of etching time. This improvement in average coulombicefficiency may be caused by more stable SEI layer in exemplary WiTnanostructures with 18 seconds of etching time due to the lessgeneration of cracks within the multiple cycles oflithiation/delithiation process. Besides, the average coulombicefficiencies may be further enhanced by increasing the cycle numbers,pre-lithiation, surface treatments of nanostructures and electrolytemodifications. Therefore, high specific capacity, coulombic efficiency,and remarkable capacity retention may be obtained under the combinedaction of the one-dimensional SiNW in porous alumina nanotubearchitecture and optimized hollow spaces of the exemplary WiTnanostructure.

While the foregoing has described what may be considered to be the bestmode and/or other examples, it is understood that various modificationsmay be made therein and that the subject matter disclosed herein may beimplemented in various forms and examples, and that the teachings may beapplied in numerous applications, only some of which have been describedherein. It is intended by the following claims to claim any and allapplications, modifications and variations that fall within the truescope of the present teachings.

Unless otherwise stated, all measurements, values, ratings, positions,magnitudes, sizes, and other specifications that are set forth in thisspecification, including in the claims that follow, are approximate, notexact. They are intended to have a reasonable range that is consistentwith the functions to which they relate and with what is customary inthe art to which they pertain.

The scope of protection is limited solely by the claims that now follow.That scope is intended and should be interpreted to be as broad as isconsistent with the ordinary meaning of the language that is used in theclaims when interpreted in light of this specification and theprosecution history that follows and to encompass all structural andfunctional equivalents. Notwithstanding, none of the claims are intendedto embrace subject matter that fails to satisfy the requirement ofSections 101, 102, or 103 of the Patent Act, nor should they beinterpreted in such away. Any unintended embracement of such subjectmatter is hereby disclaimed.

Except as stated immediately above, nothing that has been stated orillustrated is intended or should be interpreted to cause a dedicationof any component, step, feature, object, benefit, advantage, orequivalent to the public, regardless of whether it is or is not recitedin the claims.

It will be understood that the terms and expressions used herein havethe ordinary meaning as is accorded to such terms and expressions withrespect to their corresponding respective areas of inquiry and studyexcept where specific meanings have otherwise been set forth herein.Relational terms such as first and second and the like may be usedsolely to distinguish one entity or action from another withoutnecessarily requiring or implying any actual such relationship or orderbetween such entities or actions. The terms “comprises,” “comprising,”or any other variation thereof, are intended to cover a non-exclusiveinclusion, such that a process, method, article, or apparatus thatcomprises a list of elements does not include only those elements butmay include other elements not expressly listed or inherent to suchprocess, method, article, or apparatus. An element proceeded by “a” or“an” does not, without further constraints, preclude the existence ofadditional identical elements in the process, method, article, orapparatus that comprises the element.

The Abstract of the Disclosure is provided to allow the reader toquickly ascertain the nature of the technical disclosure. It issubmitted with the understanding that it will not be used to interpretor limit the scope or meaning of the claims. In addition, in theforegoing Detailed Description, it can be seen that various features aregrouped together in various implementations. This is for purposes ofstreamlining the disclosure and is not to be interpreted as reflectingan intention that the claimed implementations require more features thanare expressly recited in each claim. Rather, as the following claimsreflect, the inventive subject matter lies in less than all features ofa single disclosed implementation. Thus, the following claims are herebyincorporated into the Detailed Description, with each claim standing onits own as a separately claimed subject matter.

While various implementations have been described, the description isintended to be exemplary, rather than limiting and it will be apparentto those of ordinary skill in the art that many more implementations andimplementations are possible that are within the scope of theimplementations. Although many possible combinations of features areshown in the accompanying figures and discussed in this detaileddescription, many other combinations of the disclosed features arepossible. Any feature of any implementation may be used in combinationwith or substituted for any other feature or element in any otherimplementation unless specifically restricted. Therefore, it will beunderstood that any of the features shown and/or discussed in thepresent disclosure may be implemented together in any suitablecombination. Accordingly, the implementations are not to be restrictedexcept in the light of the attached claims and their equivalents. Also,various modifications and changes may be made within the scope of theattached claims.

What is claimed is:
 1. A method for fabricating porous wire-in-tube(WiT) nanostructures, comprising: forming a first porous core-shellnanostructure, forming the first porous core-shell nanostructurecomprising: forming a porous layer on a semi-conductive core bydepositing a first plurality of particles on the semi-conductive core,forming the porous layer comprising obtaining a plurality of unmaskedregions, each of the plurality of unmasked regions comprising a portionof a surface of the semi-conductive core, the surface not covered withone or more of the first plurality of particles; and generating aninitial porous semi-conductive core of the first porous core-shellnanostructure by etching the plurality of unmasked regions of thesemi-conductive core simultaneously with forming the porous layer;forming a second porous core-shell nanostructure comprising increasingthickness and porosity of the first porous core-shell nanostructure byrepeating an iterative process until the thickness of the porous layerreaches a predefined threshold, the iterative process comprising:increasing the thickness of the porous layer by depositing a secondplurality of particles on the initial porous semi-conductive core; andgenerating a secondary porous semi-conductive core of the second porouscore-shell nanostructure by etching the plurality of unmasked regions ofthe initial porous semi-conductive core simultaneously with depositingthe second plurality of particles; and forming a porous WiTnanostructure by etching the secondary porous semi-conductive core ofthe second porous core-shell nanostructure.
 2. The method of claim 1,wherein depositing the first plurality of particles on thesemi-conductive core comprises: generating a plurality of metalparticles by placing a metal electrode in a plasma environment withplasma power between 100 W and 300 W; and sputtering the plurality ofmetal particles on the semi-conductive core by exposing the plurality ofmetal particles to a mixture of O₂/H₂ gases.
 3. The method of claim 2,wherein placing the metal electrode in the plasma environment comprisesplacing at least one of an aluminum (Al) electrode, and a titanium (Ti)electrode in the plasma environment.
 4. The method of claim 2, whereinexposing the plurality of metal particles to the mixture of O₂/H₂ gasescomprises introducing the mixture of O₂/H₂ gases to the plurality ofmetal particles for duration between 10 seconds and 100 seconds.
 5. Themethod of claim 1, wherein etching the plurality of unmasked regions ofthe semi-conductive core simultaneously with forming the porous layercomprises exposing the porous layer to a mixture of O₂/H₂ and afluorine-containing gas for less than 7 seconds.
 6. The method of claim1, wherein etching the plurality of unmasked regions of thesemi-conductive core simultaneously with forming the porous layercomprises introducing a mixture of O₂/H₂/SF₆ gases to the porous layer.7. The method of claim 1, wherein etching the secondary poroussemi-conductive core comprises exposing the secondary poroussemi-conductive core to a fluorine-containing gas for duration between10 seconds and 50 seconds with a flow rate between 100 sccm and 300 sccmand plasma power between 100 W and 300 W.
 8. The method of claim 1,wherein repeating the iterative process until the thickness of theporous layer reaches the predefined threshold comprises repeating theiterative process until the thickness of the porous layer reaches avalue less than 1000 nm.
 9. The method of claim 8, wherein repeating theiterative process until the thickness of the porous layer reaches thepredefined threshold comprises repeating the iterative process until thethickness of the porous layer reaches a value between 1 nm and 20 nm.10. The method of claim 1, wherein depositing the porous layer on thesemi-conductive core comprises depositing the porous layer on at leastone of a silicon core, a germanium core, and combinations thereof. 11.The method of claim 1, wherein depositing the porous layer on thesemi-conductive core comprises depositing the porous layer withnanosized pores on the semi-conductive core.
 12. The method of claim 1,wherein depositing the porous layer on the semi-conductive corecomprises depositing the porous layer on a nanowire with a diameterbetween 10 nm and 500 nm.
 13. A system for fabricating porouswire-in-tube (WiT) nanostructures, the system comprising: a mainchamber, comprising: a substrate holding a semi-conductive core, thesemi-conductive core comprising at least one of a silicon core and agermanium core; and a pair of parallel metal electrodes, comprising: atop electrode configured to generate a plurality of metal particles, thetop electrode comprising at least one of an aluminum (Al) electrode anda titanium (Ti) electrode; and a ground electrode configured to hold thesubstrate; and a gas source of a plurality of gas sources, the gassource configured to contain at least one gas of a plurality of gases,the plurality of gases comprising O₂, H₂, and a fluorine-containing gas,the fluorine-containing comprising sulfur hexafluoride (SF₆); a gasinlet configured to introduce a mixture of the plurality of gases intothe main chamber; a gas valve of a plurality of gas valves, the gasvalve configured to couple the gas inlet with a respective gas source ofthe plurality of gas sources; a vacuum pump configured to generate avacuum inside the main chamber; and a radiofrequency generatorconfigured to generate a plasma environment with a plasma power between100 W and 300 W in the vacuum; a memory having processor-readableinstructions stored therein; and one or more processors configured toaccess the memory and execute the processor-readable instructions,which, when executed by the one or more processors configures the one ormore processors to perform a method, the method comprising: forming afirst porous core-shell nanostructure, forming the first porouscore-shell nanostructure comprising: forming a porous layer on asemi-conductive core by depositing a first plurality of particles on thesemi-conductive core, forming the porous layer comprising obtaining aplurality of unmasked regions, each of the plurality of unmasked regionscomprising a portion of a surface of the semi-conductive core, thesurface not covered with one or more of the first plurality ofparticles; and generating an initial porous semi-conductive core byetching the plurality of unmasked regions of the semi-conductive coresimultaneously with forming the porous layer; forming a second porouscore-shell nanostructure comprising increasing thickness and porosity ofthe first porous core-shell nanostructure by repeating an iterativeprocess until the thickness of the porous layer reaches a predefinedthreshold, the iterative process comprising: increasing the thickness ofthe porous layer by depositing a second plurality of particles on thesemi-conductive core; and generating a secondary porous semi-conductivecore by etching the plurality of unmasked regions of the semi-conductivecore simultaneously with depositing the second plurality of particles;and forming a porous WiT nanostructure by etching the secondary poroussemi-conductive core.
 14. The system of claim 13, wherein depositing thefirst plurality of particles on the semi-conductive core comprises:generating a plurality of metal particles by placing the top electrodein the plasma environment; and sputtering the plurality of metalparticles on the semi-conductive core, comprising introducing a mixtureof O₂ and H₂ to the plurality of metal particles for duration between 10seconds and 100 seconds by adjusting each respective gas valve of theplurality of gas valves.
 15. The system of claim 13, wherein etching theplurality of unmasked regions of the semi-conductive core simultaneouslywith depositing the porous layer comprises introducing a mixture of O₂,H₂, and a fluorine-containing gas to the porous layer for duration lessthan 7 seconds by adjusting each respective gas valve of the pluralityof gas valves.
 16. The system of claim 13, wherein etching the secondaryporous semi-conductive core comprises introducing thefluorine-containing gas to the secondary porous semi-conductive corewith a flow rate between 100 sccm and 300 sccm for duration between 10seconds and 50 seconds by adjusting each respective gas valve of theplurality of gas valves.
 17. A wire-in-tube nanostructure, comprising: aporous nanotube; a semi-conductive nanowire embedded inside the porousnanotube; and a gap between the porous nanotube and the semi-conductivenanowire.
 18. The wire-in-tube nanostructure of claim 17, wherein: theporous nanotube has a thickness between 1 nm and 20 nm; and thesemi-conductive nanowire has a diameter between 10 nm and 500 nm. 19.The wire-in-tube nanostructure of claim 17, wherein: the porous nanotubecomprises at least one of alumina, titanium dioxide, and combinationsthereof; and the semi-conductive nanowire comprises at least one ofsilicon, germanium, and combinations thereof.
 20. The wire-in-tubenanostructure of claim 17, wherein: the porous nanotube comprises anamorphous structure; and the semi-conductive nanowire comprises acrystalline structure.